The present invention relates to a semiconductor memory such as a DRAM and particularly relates to a counter circuit for automatically generating a column address within the memory in a high-speed mode.
A DRAM, one type of a semiconductor memory can operate in first page mode, extended data output (EDO) mode and pipelined burst mode (PBM) no that data may be transferred at high speed between it and a CPU which operates at high speed. Recently, a synchronous DRAM has been developed which operates at high speed.
A DRAM operates in PBM as is illustrated in FIG. 1A. A synchronous DRAM operates as is shown in FIG. 1B. In both the DRAM and the synchronous DRAM, a column address is generated from a column address signal (CA1) which has been fetched from an external device. In the DRAM, a column address strobe signal /CAS at "1" level is set at "0" level. In the synchronous DRAM, a clock signal CLK at "0" level is set at "1" level. The data signals are thereby continuously read from the DRAM and the synchronous DRAM a plurality of times (D1-1, D-2, . . . ). This data-reading scheme is called "burst read". Generally, the burst length is set at 1, 2, 4, 8, . . . , or 2.sup.n by using a mode register.
FIG. 2 shows a conventional counter circuit designed to generate a column address which is used to operate a DRAM or a synchronous DRAM, thereby to accomplish burst read (or burst write). The counter circuit is a four-bit circuit, that is, has a burst length of 16. It consists of four D-type flip-flop circuits 101 to 104, four Exclusive-NOR gate circuits 105 to 108 three NAND gate circuits 109 to 111 and three inverters 112 to 114. A clock signal CLK is supplied to a synchronization signal input terminal in each D-type flip-flop circuit.
In FIG. 2, as regards n-th bit, the input terminal D of the D-type flip flop circuit is supplied with the output signal EXNORn (n=1, 2, . . . ) of the corresponding n-th bit Exclusive-NOR gate circuit. The output Q of the D-type flip-flop circuit is outputted as a count signal Qn of the n-th bit. To one of the input terminals of the Exclusive-NOR gate circuit, the count signal Qn of the corresponding n-th bit D-type flip-flop circuit is supplied. To the other input terminal thereof, an output signal of the corresponding n-th bit NAND gate circuit is supplied. To one of the input terminals of NAND gate circuit, the output signal Qn-1 of the (n-1)th bit D-type flip-flop circuit is supplied. The output signal of the (n-1)-th bit Exclusive NOR gate circuit is supplied to the other input terminal of the NAND gate circuit through the corresponding n-th bit inverter. As regards the first bit, neither an NAND gate circuit nor an inverter is provided and a ground potential VSS ("0" level) is supplied to the other input terminal of the Exclusive-NOR gate circuit.
In the counter circuit of such an arrangement, count signals Q1 to Q4 are sequentially changed synchronously with a clock signal CLU as indicated by the timing chart of FIG. 3. FIG. 3 illustrates a case where counting starts from the count number 0 where Q1 to Q 4 are all at "0" level. At this time, "0" level is supplied to the other input terminal of the first bit Exclusive-NOR gate circuit 105. Therefore, if the count signal Q1 supplied to one input terminal of the Exclusive-NOR gate circuit 105 is "0" level, the output signal EXNOR 1 is "0" level. From this, it is understood that the first bit flip-flop circuit 101 to which input terminal D the signal EXNOR 1 is supplied to, outputs a signal at a level opposite to that of a one-cycle prior output every time the clock signal CLK turns to "1" level. In other words, as shown in FIG. 3, the count signal Q1 advances by half a cycle of the clock signal CLK.
Meanwhile, an output signal EXNOR2 of the second bit Exclusive-NOR gate circuit 106 is inverted every time the signal EXNOR2 turns to "0" level. The output signal EXNOR2 of the second bit flip-flop circuit 102, to which input terminal D the signal EXNOR 2 is supplied, consequently advances by half a cycle of the signal Q1 changed in the same cycle as that of the signal EXNOR2. Likewise, an output signal Q3 of the third bit flip-flop circuit 103 advances by half a cycle of the output signal Q2 of the second bit flip-flop circuit 102. An output signal Q4 of the fourth bit flip-flop circuit 104 advances by half a cycle of the output signal Q3 of the third bit flip flop circuit 103. Therefore, it the count signals Q1 to Q4 of the flip-flop circuits 101 to 104 are based on the binary system, the count circuit conducts four-bit-length upcount operation while using the clock signal CLK as a synchronization signal.
Such sequence where the count number is sequentially increased is referred to as linear sequence. In the linear sequence, the count number is increased one by one as long as a clock signal continues to be supplied.
In the meantime, the above-described conventional counter circuit is only applicable to linear sequence. The PBM or a burst read (or burst write) of a synchronous DRAM requires count operation referred to as interleave sequence in addition to the linear sequence mentioned above. The conventional counter circuit, however, cannot be applied to the interleave sequence and therefore another counter circuit dedicated to the interleave sequence is required.
To effect burst read (or burst write), the burst operation must be terminated upon detecting that the column address has been generated for the burst length. To start the burst operation again, a new column address must be fetched from the external device. Hence, it is necessary to detect whether or not the count of the column counter has reached a predetermined value.